# TCL File Generated by Component Editor 10.1
# Thu Jan 06 14:09:23 CST 2011
# DO NOT MODIFY


# +-----------------------------------
# | 
# | TERASIC_ADC_READ "TERASIC_ADC_READ" v1.0
# | null 2011.01.06.14:09:23
# | TERASIC_ADC_READ
# | 
# | D:/DE_NANO/DE_NANO_SOPC_ADC_IP/ip/TERASIC_ADC_READ/TERASIC_ADC_READ.v
# | 
# |    ./TERASIC_ADC_READ.v syn, sim
# |    ./ADC_READ.vhd syn, sim
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.1
# | 
package require -exact sopc 10.1
# | 
# +-----------------------------------

# +-----------------------------------
# | module TERASIC_ADC_READ
# | 
set_module_property DESCRIPTION TERASIC_ADC_READ
set_module_property NAME TERASIC_ADC_READ
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Terasic Technologies Inc."
set_module_property DISPLAY_NAME TERASIC_ADC_READ
set_module_property TOP_LEVEL_HDL_FILE TERASIC_ADC_READ.v
set_module_property TOP_LEVEL_HDL_MODULE TERASIC_ADC_READ
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file TERASIC_ADC_READ.v {SYNTHESIS SIMULATION}
add_file ADC_READ.vhd {SYNTHESIS SIMULATION}
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clock
# | 
add_interface clock clock end
set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

add_interface_port clock clk clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point reset
# | 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT

set_interface_property reset ENABLED true

add_interface_port reset reset_n reset_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point slave
# | 
add_interface slave avalon end
set_interface_property slave addressAlignment NATIVE
set_interface_property slave addressUnits WORDS
set_interface_property slave associatedClock clock
set_interface_property slave associatedReset reset
set_interface_property slave burstOnBurstBoundariesOnly false
set_interface_property slave explicitAddressSpan 0
set_interface_property slave holdTime 0
set_interface_property slave isMemoryDevice false
set_interface_property slave isNonVolatileStorage false
set_interface_property slave linewrapBursts false
set_interface_property slave maximumPendingReadTransactions 0
set_interface_property slave printableDevice false
set_interface_property slave readLatency 0
set_interface_property slave readWaitTime 1
set_interface_property slave setupTime 0
set_interface_property slave timingUnits Cycles
set_interface_property slave writeWaitTime 0

set_interface_property slave ENABLED true

add_interface_port slave s_chipselect chipselect Input 1
add_interface_port slave s_read read Input 1
add_interface_port slave s_readdata readdata Output 16
add_interface_port slave s_write write Input 1
add_interface_port slave s_writedata writedata Input 16
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point conduit_end
# | 
add_interface conduit_end conduit end

set_interface_property conduit_end ENABLED true

add_interface_port conduit_end SPI_OUT export Output 1
add_interface_port conduit_end SPI_IN export Input 1
add_interface_port conduit_end SPI_CS_n export Output 1
add_interface_port conduit_end SPI_CLK export Output 1
# | 
# +-----------------------------------
