# TCL File Generated by Component Editor 10.1
# Sat Jan 15 23:49:05 CST 2011
# DO NOT MODIFY


# +-----------------------------------
# | 
# | TERASIC_SPI_3WIRE "TERASIC_SPI_3WIRE" v1.0
# | null 2011.01.15.23:49:05
# | TERASIC_SPI_3WIRE
# | 
# | D:/DE_NANO/DE_NANO_SOPC_DEMO/ip/TARASIC_SPI_3WIRE/TERASIC_SPI_3WIRE.v
# | 
# |    ./TERASIC_SPI_3WIRE.v syn, sim
# |    ./SPI_3WIRE.v syn, sim
# |    ./gsensor_fifo.v syn, sim
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.1
# | 
package require -exact sopc 10.1
# | 
# +-----------------------------------

# +-----------------------------------
# | module TERASIC_SPI_3WIRE
# | 
set_module_property DESCRIPTION TERASIC_SPI_3WIRE
set_module_property NAME TERASIC_SPI_3WIRE
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Terasic Technologies Inc."
set_module_property DISPLAY_NAME TERASIC_SPI_3WIRE
set_module_property TOP_LEVEL_HDL_FILE TERASIC_SPI_3WIRE.v
set_module_property TOP_LEVEL_HDL_MODULE TERASIC_SPI_3WIRE
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file TERASIC_SPI_3WIRE.v {SYNTHESIS SIMULATION}
add_file SPI_3WIRE.v {SYNTHESIS SIMULATION}
add_file gsensor_fifo.v {SYNTHESIS SIMULATION}
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clock_reset
# | 
add_interface clock_reset clock end
set_interface_property clock_reset clockRate 0

set_interface_property clock_reset ENABLED true

add_interface_port clock_reset clk clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clock_reset_reset
# | 
add_interface clock_reset_reset reset end
set_interface_property clock_reset_reset associatedClock clock_reset
set_interface_property clock_reset_reset synchronousEdges DEASSERT

set_interface_property clock_reset_reset ENABLED true

add_interface_port clock_reset_reset reset_n reset_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point slave
# | 
add_interface slave avalon end
set_interface_property slave addressAlignment NATIVE
set_interface_property slave addressUnits WORDS
set_interface_property slave associatedClock clock_reset
set_interface_property slave associatedReset clock_reset_reset
set_interface_property slave burstOnBurstBoundariesOnly false
set_interface_property slave explicitAddressSpan 0
set_interface_property slave holdTime 0
set_interface_property slave isMemoryDevice false
set_interface_property slave isNonVolatileStorage false
set_interface_property slave linewrapBursts false
set_interface_property slave maximumPendingReadTransactions 0
set_interface_property slave printableDevice false
set_interface_property slave readLatency 1
set_interface_property slave readWaitStates 0
set_interface_property slave readWaitTime 0
set_interface_property slave setupTime 0
set_interface_property slave timingUnits Cycles
set_interface_property slave writeWaitTime 0

set_interface_property slave ENABLED true

add_interface_port slave s_chipselect chipselect Input 1
add_interface_port slave s_address address Input 4
add_interface_port slave s_write write Input 1
add_interface_port slave s_writedata writedata Input 8
add_interface_port slave s_read read Input 1
add_interface_port slave s_readdata readdata Output 8
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point conduit_end
# | 
add_interface conduit_end conduit end

set_interface_property conduit_end ENABLED true

add_interface_port conduit_end SPI_SDIO export Bidir 1
add_interface_port conduit_end SPI_SCLK export Output 1
add_interface_port conduit_end SPI_CS_n export Output 1
# | 
# +-----------------------------------
